IEDM: Samsung makes 3nm gate-all-around CMOS

October 29, 2018 // By Peter Clarke
A paper from researchers at Samsung describing a 3nm CMOS IC manufacturing process with gate-all-around (GAA) transistors, has been accepted as a late paper at the upcoming International Electron Devices Meeting (IEDM).

IEDM takes place December 1 to 5 in San Francisco, California.

Samsung had announced earlier this year that its 3nm process will come in two variants – 3GAAE and 3GAAP – standing for early and plus and will be based on the nanosheet construction with multiple (three) lateral ribbon-shaped wires in a fin (see Samsung to introduce nanosheet transistors in 3nm node ).

According to the paper abstract the GAA transistor channels comprising the horizontal nanosheets that are completely surrounded by gate structures. Samsung calls this a Multi-Bridge-Channel (MBC) architecture, and says it is highly manufacturable as it makes use of  approximately 90 percent of the company’s existing FinFET fabrication technology, requiring only a few revised photomasks.

As yet the technology appears to be a single layer structure with n- and p-type transistors expected to sit side by side.

The paper reports on the performance of a fully functioning SRAM macro manufactured using the process. The process provides a 65mV/decade sub-threshold swing, an on-current that is 31 percent higher than the company's current FinFET technology and offers design flexibility because the nanosheet channel widths can be varied by means of direct patterning.

Paper #28.7 is titled ' 3nm GAA Technology Featuring Multi-Bridge-Channel FET for Low-Power and High-Performance Applications ,' and authored by G. Bae et alia, Samsung.

Related links and articles:

www.ieee-iedm.org

www.samsung.com

News articles:

Samsung to introduce nanosheet transistors in 3nm node

IMEC presents 'n-over-p' complementary FET proposal

IEDM: Intel embeds MRAM in FinFET process


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