Mythic AI adopts RISC-V core from Codasip

December 10, 2018 // By Peter Clarke
Machine-learning chip developer Mythic Inc. (Austin, Texas) has selected the configurable Bk5 RISC-V processor from Codasip Ltd. (Brno, Czech Republic) for use in future neural networking chips.

Mythic was founded in 2012 as Isocline Engineering Corp. and is adopting an analog "processing-in-memory" approach to neural network implementation

The Mythic Intelligence Processing Unit (IPU), which performs the inference step of deep neural networks inside the same flash memory array which stores the neural network’s weights and thereby delivers advantages in performance, cost, and power consumption compared with some more traditional systems that build inference processors in logic and move data to and from these processors.

A similar approach is being adopted by Anaflash Inc. (see Embedded flash memory hosts machine learning ).

"We chose Codasip's Bk5 RISC-V processor and Codasip Studio for our PCIe-attached IPU deep learning accelerator because it gave us the flexibility to create a truly unique processor that was specific to our needs, while maintaining compliance to the RISC-V standard," stated Ty Garibay, vice president of hardware engineering at Mythic, in a statement. "While we have the expertise to build our own RISC-V processor, we determined that Codasip Studio, with its automatic generation of both verified hardware and fully compatible software tool-chain, was a more efficient approach and allowed us to focus on other critical areas of the product development."

The Codasip Bk5 processor, based on the RISC-V open instruction set architecture (ISA) definition, features a single 5-stage in-order execution processor pipeline and offers optional caches, IEEE 1149.1 debug, branch prediction, and industry standard bus interfaces. Further, the Bk5 – like all Codasip RISC-V implementations – is configurable and extensible.

With Codasip Studio, designers can begin with a high-level description of a RISC-V micro-architectural implementation defined and delivered by Codasip, and then describe their desired architectural and ISA modifications in the CodAL architecture description language, and then automatically synthesize the design’s RTL, testbench, virtual platform models and processor SDK comprising C/C++ compiler, debugger, profiler, and other parts.

Codasip was founded in 2006 and was a founding member of the RSIC-V Foundation.

Codasip has raised $10 million


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