Synopsys models IMEC complementary FET

December 11, 2018 // By Peter Clarke
EDA company Synopsys Inc. (Mountain View, Calif.) has completed the modelling of parasitic variation and delay sensitivity in sub-3nm complementary FET (CFET) architectures proposed by research institute IMEC.

The CFET is a development of the stacked gate all around (GAA) nanowire form of transistor in which either n- or p-type GAAs are stacked above the other type so that two transistors occupy the space of one and CMOS logic circuitry can be supported efficiently.

IMEC claims its proposed CFET can eventually outperform FinFETs and meet the N3 requirements for power and performance. Synsopsys said collaboration with IMEC would continue to ramp-up advances towards 2nm.

In both 3nm and 2nm process technologies the variation of middle-of-line parameters increases significantly due to the high resistence of metal lines, vias and surface scattering, Synsopsys said. Synopsys and IMEC used the QuickCap NX 3D field solver to model parasitics for a variety of device architectures and to identify the most critical device dimensions and properties.

"Imec is at the forefront of research into semiconductor technology. Our collaboration with imec to develop variation-aware solutions down to 2 nanometer processes will benefit the entire semiconductor industry," said Antun Domic, chief technology officer at Synopsys, in a statement.

Related links and articles:

www.synopsys.com

News articles:

IMEC presents 'n-over-p' complementary FET proposal

IMEC, Cadence tape-out first 3nm test chip

Synopsys buys Glasgow EDA startup


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